Implementasi Digital Lock-in Amplifier Dua Kanal Berbasis FPGA untuk Pengukuran Magnitudo dan Beda Fasa

Hardian Tri Pamungkas, Isnan Nur Rifa’i, S.Si., M.Eng., Ph.D.

2026 | Tugas Akhir | D4 Teknologi Rekayasa Instrumentasi dan Kontrol

Pengukuran magnitudo dan beda fasa antar sinyal secara presisi sangat dibutuhkan dalam aplikasi instrumentasi seperti spektroskopi bioimpedansi dan tomografi impedansi listrik. Penelitian ini mengimplementasikan Digital Lock-In Amplifier (DLIA) dua kanal berbasis FPGA Intel Cyclone V SoC (5CSEMA4U23C6) dengan dua ADC eksternal AD9254 14-bit (150 MSPS). Seluruh rantai pemrosesan sinyal—meliputi penyelarasan data melalui FIFO asinkron, demodulasi kuadratur I/Q berbasis NCO 32-bit (100 kHz), penapis integrate-and-dump (1500 sampel), serta ekstraksi magnitudo dan fasa menggunakan CORDIC 16-tahap—diimplementasikan sepenuhnya di level perangkat keras (pure hardware). Data hasil pengukuran ditransmisikan ke komputer host melalui Ethernet TCP/IP. Pengujian menunjukkan linearitas magnitudo yang sangat baik (R² ? 1,000; INL < 0>phase mismatch antar kanal sebesar 0,050°. Dengan konsumsi sumber daya hanya 23% ALM, sistem ini terbukti memiliki efisiensi tinggi serta performa presisi yang memenuhi kebutuhan aplikasi instrumentasi medis

Bioimpedance spectroscopy and electrical impedance tomography both rely on measuring the magnitude and phase difference between two signals with sub-degree accuracy. This paper describes a two-channel DLIA built on an Intel Cyclone V SoC FPGA (5CSEMA4U23C6) with two AD9254 14-bit ADCs running at 150 MSPS each. The full processing chain runs in hardware: inter-channel alignment via an asynchronous Gray-pointer FIFO, quadrature I/Q demodulation against a 32-bit NCO at 100 kHz, a 1500-sample integrate-and-dump filter, and a 16-stage CORDIC for magnitude and phase extraction. No soft processor sits in the signal path. Processed data are streamed to a host PC over TCP/IP Ethernet via a W5500 module. Over a 0.3 to 1.0 Vpp input sweep, magnitude linearity holds at R² ? 1.000 with INL below 0.08%. SNR gains reach +13.35 dB on the measurement channel and +10.71 dB on the reference. Phase error is a fixed +0.501° offset traceable to cable propagation delay, with random variation under 0.020°; inter-channel phase mismatch is 0.050°. Resource use sits at 23% ALM, leaving room for future expansion.

Kata Kunci : Digital Lock-in Amplifier, FPGA, Demodulasi Kuadratur, CORDIC, Pengukuran Beda Fasa, Clock Domain Crossing